Memory devices for digital computers are made up of many individual memory cells arranged in an array. Each memory cell is adapted to store one bit of information. In a traditional memory cell array, groups of individual memory cells are arranged in columns with the individual cells in each column connected together by two conductors referred to as bit lines. Such a memory array may include many columns of memory cells, each column including a bit line pair. Each memory cell is commonly made up of six transistors, two access transistors and a cross-coupled memory latch including four transistors. The memory latch includes a first node connected to the first bit line through one access transistor, and a second node connected to a second bit line through the second access transistor. The access transistors of each memory cell in a traditional memory array are connected to a single conductor referred to as a word line. The memory array includes a number of word lines, each word line commonly connecting memory cells in a row across the different columns making up the array. The word lines are used to activate the access transistors of a particular memory cell for a read operation from the cell or a write operation to the cell.
The bit lines associated with a particular memory cell in a column of a memory array are used to write a bit of information to the memory cell and are also used to read information from the cell. In a traditional write operation, the particular cell in the column is selected using the word line associated with the cell and then a desired differential charge state representing a bit of information is applied to the bit line pair associated with the selected cell. The differential charge state comprises a high-level voltage signal on one bit line and a low-level voltage signal on the other bit line of the pair. A high-level voltage signal on one bit line of the pair and a low-level voltage signal on the opposite bit line represents a "1", while the opposite charge states on the bit line pair represents a "0". The memory cell stores the desired bit of data by maintaining a high charge state at one node in the memory cell and a low charge state at the other node in the cell once the access transistors are turned off or deactivated.
In a traditional read operation, a bit of information stored in a memory cell is read from the cell using the bit line pair connected to the cell, a column decoder, and a sense amplifier. The column decoder is connected to each bit line pair in the memory array and operates to select the bit line pair associated with the memory cell from which data is to be read. Before a read operation, the bit lines associated with the desired cell are both pre-charged to a high voltage level or charge state. In the read operation, the desired memory cell is selected using the word line associated with the cell to activate the access transistors of the cell. Activating the two access transistors enables the cell to apply the stored charge states to the bit lines associated with the cell. When the charge states stored by the cell are applied to the two bit lines, the voltage on one bit line remains at the high-level voltage while the voltage on the other bit line drifts to a lower voltage level. When a sufficient voltage differential develops between the bit lines, the sense amplifier converts signals on the selected bit lines to digital signals representing the data which was stored by the memory cell.
Thus, in traditional memory arrays, data was both written to and read from a memory cell as differential signals. The differential signals comprise a high charge state on one bit line and a low charge state on the opposite bit line. This differential form of data required the simultaneous use of both bit lines in the read and write operations.
A dual port memory cell is another type of prior art memory cell. A dual port memory cell may include a six-transistor arrangement which allows data to be read from a particular cell utilizing a single bit line of the bit line pair. In memory arrays made up of these dual port memory cells, the access transistors of each memory cell were coupled to a separate word line so that the access transistors were each independently controllable. These memory arrays could also be divided up into segments or sub-arrays. Each column of memory cells in a sub-array was connected to a local bit line pair and was associated with a local column decoder or multiplexing arrangement, a local read circuit, and a local write circuit. The local read circuits of the various sub-arrays were each connected to two global "data out" lines, while the local write circuits of the various sub-arrays were each connected to a global "data in" bit line pair.
Since the access transistors in this type of dual port memory cell were independently controllable through their respective word line, each access transistor could be used as an independent access port to read the charge state from a single node of a memory cell in the array. This single charge state, also referred to as a single-ended or non-differential signal, indicated the data stored by the particular cell. Since data could be read using a single bit line of the bit line pair, an array made up of these dual port memory cells could perform two read operations at the same time.
However, data was written to the dual port memory cells using differential signals. The write operation was accomplished by turning on both access transistors and applying differential signals to the cell in the form of a high charge state on one bit line and a low charge state on the opposite bit line. Since both bit lines were used simultaneously in a write operation, no part of a write operation could be performed during a read operation even though only one bit line was required for reading data from a memory cell in the array. Also, in a multiple sub-array arrangement using the six transistor dual port memory cells, the differential signals had to be sent across the global "data in" bit lines to each sub-array. This increased the wire count and space required for the memory array.